/*
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/

/**********************************************************************************************************************
 * File Name    : sysc_iobitmask.h
 * Version      : 1.00
 * Description  : IO bit mask file for sysc.
 *********************************************************************************************************************/

#ifndef SYSC_IOBITMASK_H
#define SYSC_IOBITMASK_H

#define R_SYSC_SYS_MSTACCCTL0_SXMDMC_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL0_SXMDMC_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL0_SXMDMC_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL0_SXMDMC_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL0_SXMDMC_AWSEL_Msk                 (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL0_SXMDMC_AWSEL_Pos                 (3UL)
#define R_SYSC_SYS_MSTACCCTL0_SXMDMC_ARPU_Msk                  (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL0_SXMDMC_ARPU_Pos                  (4UL)
#define R_SYSC_SYS_MSTACCCTL0_SXMDMC_ARNS_Msk                  (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL0_SXMDMC_ARNS_Pos                  (5UL)
#define R_SYSC_SYS_MSTACCCTL0_SXMDMC_ARSEL_Msk                 (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL0_SXMDMC_ARSEL_Pos                 (7UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC00_AWPU_Msk                (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC00_AWPU_Pos                (8UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC00_AWNS_Msk                (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC00_AWNS_Pos                (9UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC00_AWSEL_Msk               (0x00000800UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC00_AWSEL_Pos               (11UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC00_ARPU_Msk                (0x00001000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC00_ARPU_Pos                (12UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC00_ARNS_Msk                (0x00002000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC00_ARNS_Pos                (13UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC00_ARSEL_Msk               (0x00008000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC00_ARSEL_Pos               (15UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC1_AWPU_Msk                 (0x00010000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC1_AWPU_Pos                 (16UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC1_AWNS_Msk                 (0x00020000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC1_AWNS_Pos                 (17UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC1_AWSEL_Msk                (0x00080000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC1_AWSEL_Pos                (19UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC1_ARPU_Msk                 (0x00100000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC1_ARPU_Pos                 (20UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC1_ARNS_Msk                 (0x00200000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC1_ARNS_Pos                 (21UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC1_ARSEL_Msk                (0x00800000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXADMC1_ARSEL_Pos                (23UL)
#define R_SYSC_SYS_MSTACCCTL0_SXRDMC0_AWPU_Msk                 (0x01000000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXRDMC0_AWPU_Pos                 (24UL)
#define R_SYSC_SYS_MSTACCCTL0_SXRDMC0_AWNS_Msk                 (0x02000000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXRDMC0_AWNS_Pos                 (25UL)
#define R_SYSC_SYS_MSTACCCTL0_SXRDMC0_AWSEL_Msk                (0x08000000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXRDMC0_AWSEL_Pos                (27UL)
#define R_SYSC_SYS_MSTACCCTL0_SXRDMC0_ARPU_Msk                 (0x10000000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXRDMC0_ARPU_Pos                 (28UL)
#define R_SYSC_SYS_MSTACCCTL0_SXRDMC0_ARNS_Msk                 (0x20000000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXRDMC0_ARNS_Pos                 (29UL)
#define R_SYSC_SYS_MSTACCCTL0_SXRDMC0_ARSEL_Msk                (0x80000000UL)
#define R_SYSC_SYS_MSTACCCTL0_SXRDMC0_ARSEL_Pos                (31UL)
#define R_SYSC_SYS_MSTACCCTL1_SXMDMC1_AWPU_Msk                 (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL1_SXMDMC1_AWPU_Pos                 (0UL)
#define R_SYSC_SYS_MSTACCCTL1_SXMDMC1_AWNS_Msk                 (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL1_SXMDMC1_AWNS_Pos                 (1UL)
#define R_SYSC_SYS_MSTACCCTL1_SXMDMC1_AWSEL_Msk                (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL1_SXMDMC1_AWSEL_Pos                (3UL)
#define R_SYSC_SYS_MSTACCCTL1_SXMDMC1_ARPU_Msk                 (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL1_SXMDMC1_ARPU_Pos                 (4UL)
#define R_SYSC_SYS_MSTACCCTL1_SXMDMC1_ARNS_Msk                 (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL1_SXMDMC1_ARNS_Pos                 (5UL)
#define R_SYSC_SYS_MSTACCCTL1_SXMDMC1_ARSEL_Msk                (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL1_SXMDMC1_ARSEL_Pos                (7UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR80_AWPU_Msk                   (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR80_AWPU_Pos                   (0UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR80_AWNS_Msk                   (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR80_AWNS_Pos                   (1UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR80_AWSEL_Msk                  (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR80_AWSEL_Pos                  (3UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR80_ARPU_Msk                   (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR80_ARPU_Pos                   (4UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR80_ARNS_Msk                   (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR80_ARNS_Pos                   (5UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR80_ARSEL_Msk                  (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR80_ARSEL_Pos                  (7UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR81_AWPU_Msk                   (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR81_AWPU_Pos                   (8UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR81_AWNS_Msk                   (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR81_AWNS_Pos                   (9UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR81_AWSEL_Msk                  (0x00000800UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR81_AWSEL_Pos                  (11UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR81_ARPU_Msk                   (0x00001000UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR81_ARPU_Pos                   (12UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR81_ARNS_Msk                   (0x00002000UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR81_ARNS_Pos                   (13UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR81_ARSEL_Msk                  (0x00008000UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR81_ARSEL_Pos                  (15UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR8L_AWPU_Msk                   (0x00010000UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR8L_AWPU_Pos                   (16UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR8L_AWNS_Msk                   (0x00020000UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR8L_AWNS_Pos                   (17UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR8L_AWSEL_Msk                  (0x00080000UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR8L_AWSEL_Pos                  (19UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR8L_ARPU_Msk                   (0x00100000UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR8L_ARPU_Pos                   (20UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR8L_ARNS_Msk                   (0x00200000UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR8L_ARNS_Pos                   (21UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR8L_ARSEL_Msk                  (0x00800000UL)
#define R_SYSC_SYS_MSTACCCTL2_SXR8L_ARSEL_Pos                  (23UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD0_AWPU_Msk                   (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD0_AWPU_Pos                   (0UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD0_AWNS_Msk                   (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD0_AWNS_Pos                   (1UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD0_AWSEL_Msk                  (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD0_AWSEL_Pos                  (3UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD0_ARPU_Msk                   (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD0_ARPU_Pos                   (4UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD0_ARNS_Msk                   (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD0_ARNS_Pos                   (5UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD0_ARSEL_Msk                  (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD0_ARSEL_Pos                  (7UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD1_AWPU_Msk                   (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD1_AWPU_Pos                   (8UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD1_AWNS_Msk                   (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD1_AWNS_Pos                   (9UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD1_AWSEL_Msk                  (0x00000800UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD1_AWSEL_Pos                  (11UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD1_ARPU_Msk                   (0x00001000UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD1_ARPU_Pos                   (12UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD1_ARNS_Msk                   (0x00002000UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD1_ARNS_Pos                   (13UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD1_ARSEL_Msk                  (0x00008000UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD1_ARSEL_Pos                  (15UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD2_AWPU_Msk                   (0x00010000UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD2_AWPU_Pos                   (16UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD2_AWNS_Msk                   (0x00020000UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD2_AWNS_Pos                   (17UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD2_AWSEL_Msk                  (0x00080000UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD2_AWSEL_Pos                  (19UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD2_ARPU_Msk                   (0x00100000UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD2_ARPU_Pos                   (20UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD2_ARNS_Msk                   (0x00200000UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD2_ARNS_Pos                   (21UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD2_ARSEL_Msk                  (0x00800000UL)
#define R_SYSC_SYS_MSTACCCTL3_SXSD2_ARSEL_Pos                  (23UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H0_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H0_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H0_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H0_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H0_AWSEL_Msk                 (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H0_AWSEL_Pos                 (3UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H0_ARPU_Msk                  (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H0_ARPU_Pos                  (4UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H0_ARNS_Msk                  (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H0_ARNS_Pos                  (5UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H0_ARSEL_Msk                 (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H0_ARSEL_Pos                 (7UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H1_AWPU_Msk                  (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H1_AWPU_Pos                  (8UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H1_AWNS_Msk                  (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H1_AWNS_Pos                  (9UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H1_AWSEL_Msk                 (0x00000800UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H1_AWSEL_Pos                 (11UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H1_ARPU_Msk                  (0x00001000UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H1_ARPU_Pos                  (12UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H1_ARNS_Msk                  (0x00002000UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H1_ARNS_Pos                  (13UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H1_ARSEL_Msk                 (0x00008000UL)
#define R_SYSC_SYS_MSTACCCTL4_SXU3H1_ARSEL_Pos                 (15UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2H0_P0_AWPU_Msk               (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2H0_P0_AWPU_Pos               (0UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H0_P0_AWNS_Msk              (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H0_P0_AWNS_Pos              (1UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H0_P0_AWSEL_Msk             (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H0_P0_AWSEL_Pos             (3UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H0_P0_ARPU_Msk              (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H0_P0_ARPU_Pos              (4UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H0_P0_ARNS_Msk              (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H0_P0_ARNS_Pos              (5UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H0_P0_ARSEL_Msk             (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H0_P0_ARSEL_Pos             (7UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H1_P1_AWPU_Msk              (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H1_P1_AWPU_Pos              (8UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H1_P1_AWNS_Msk              (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H1_P1_AWNS_Pos              (9UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H1_P1_AWSEL_Msk             (0x00000800UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H1_P1_AWSEL_Pos             (11UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H1_P1_ARPU_Msk              (0x00001000UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H1_P1_ARPU_Pos              (12UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H1_P1_ARNS_Msk              (0x00002000UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H1_P1_ARNS_Pos              (13UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H1_P1_ARSEL_Msk             (0x00008000UL)
#define R_SYSC_SYS_MSTACCCTL5_SXHU2H1_P1_ARSEL_Pos             (15UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2F_AWPU_Msk                   (0x00010000UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2F_AWPU_Pos                   (16UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2F_AWNS_Msk                   (0x00020000UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2F_AWNS_Pos                   (17UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2F_AWSEL_Msk                  (0x00080000UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2F_AWSEL_Pos                  (19UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2F_ARPU_Msk                   (0x00100000UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2F_ARPU_Pos                   (20UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2F_ARNS_Msk                   (0x00200000UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2F_ARNS_Pos                   (21UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2F_ARSEL_Msk                  (0x00800000UL)
#define R_SYSC_SYS_MSTACCCTL5_SHU2F_ARSEL_Pos                  (23UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE0_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE0_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE0_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE0_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE0_AWSEL_Msk                 (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE0_AWSEL_Pos                 (3UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE0_ARPU_Msk                  (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE0_ARPU_Pos                  (4UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE0_ARNS_Msk                  (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE0_ARNS_Pos                  (5UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE0_ARSEL_Msk                 (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE0_ARSEL_Pos                 (7UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE1_AWPU_Msk                  (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE1_AWPU_Pos                  (8UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE1_AWNS_Msk                  (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE1_AWNS_Pos                  (9UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE1_AWSEL_Msk                 (0x00000800UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE1_AWSEL_Pos                 (11UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE1_ARPU_Msk                  (0x00001000UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE1_ARPU_Pos                  (12UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE1_ARNS_Msk                  (0x00002000UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE1_ARNS_Pos                  (13UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE1_ARSEL_Msk                 (0x00008000UL)
#define R_SYSC_SYS_MSTACCCTL6_SXGBE1_ARSEL_Pos                 (15UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI0_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI0_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI0_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI0_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI0_AWSEL_Msk                 (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI0_AWSEL_Pos                 (3UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI0_ARPU_Msk                  (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI0_ARPU_Pos                  (4UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI0_ARNS_Msk                  (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI0_ARNS_Pos                  (5UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI0_ARSEL_Msk                 (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI0_ARSEL_Pos                 (7UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI1_AWPU_Msk                  (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI1_AWPU_Pos                  (8UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI1_AWNS_Msk                  (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI1_AWNS_Pos                  (9UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI1_AWSEL_Msk                 (0x00000800UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI1_AWSEL_Pos                 (11UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI1_ARPU_Msk                  (0x00001000UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI1_ARPU_Pos                  (12UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI1_ARNS_Msk                  (0x00002000UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI1_ARNS_Pos                  (13UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI1_ARSEL_Msk                 (0x00008000UL)
#define R_SYSC_SYS_MSTACCCTL7_SXPCI1_ARSEL_Pos                 (15UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRV0_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRV0_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRV0_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRV0_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRS0_AWPU_Msk                  (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRS0_AWPU_Pos                  (8UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRS0_AWNS_Msk                  (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRS0_AWNS_Pos                  (9UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRV1_AWPU_Msk                  (0x00010000UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRV1_AWPU_Pos                  (16UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRV1_AWNS_Msk                  (0x00020000UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRV1_AWNS_Pos                  (17UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRS1_AWPU_Msk                  (0x01000000UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRS1_AWPU_Pos                  (24UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRS1_AWNS_Msk                  (0x02000000UL)
#define R_SYSC_SYS_MSTACCCTL8_SXCRS1_AWNS_Pos                  (25UL)
#define R_SYSC_SYS_MSTACCCTL9_SXCRV2_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL9_SXCRV2_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL9_SXCRV2_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL9_SXCRV2_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL9_SXCRV3_AWPU_Msk                  (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL9_SXCRV3_AWPU_Pos                  (8UL)
#define R_SYSC_SYS_MSTACCCTL9_SXCRV3_AWNS_Msk                  (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL9_SXCRV3_AWNS_Pos                  (9UL)
#define R_SYSC_SYS_MSTACCCTL10_SXISF_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL10_SXISF_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL10_SXISF_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL10_SXISF_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL10_SXIST_AWPU_Msk                  (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL10_SXIST_AWPU_Pos                  (8UL)
#define R_SYSC_SYS_MSTACCCTL10_SXIST_AWNS_Msk                  (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL10_SXIST_AWNS_Pos                  (9UL)
#define R_SYSC_SYS_MSTACCCTL10_SXIST_ARPU_Msk                  (0x00001000UL)
#define R_SYSC_SYS_MSTACCCTL10_SXIST_ARPU_Pos                  (12UL)
#define R_SYSC_SYS_MSTACCCTL10_SXIST_ARNS_Msk                  (0x00002000UL)
#define R_SYSC_SYS_MSTACCCTL10_SXIST_ARNS_Pos                  (13UL)
#define R_SYSC_SYS_MSTACCCTL10_SXISV_ARPU_Msk                  (0x00100000UL)
#define R_SYSC_SYS_MSTACCCTL10_SXISV_ARPU_Pos                  (20UL)
#define R_SYSC_SYS_MSTACCCTL10_SXISV_ARNS_Msk                  (0x00200000UL)
#define R_SYSC_SYS_MSTACCCTL10_SXISV_ARNS_Pos                  (21UL)
#define R_SYSC_SYS_MSTACCCTL11_SXISU_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL11_SXISU_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL11_SXISU_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL11_SXISU_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL11_SXISU_ARPU_Msk                  (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL11_SXISU_ARPU_Pos                  (4UL)
#define R_SYSC_SYS_MSTACCCTL11_SXISU_ARNS_Msk                  (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL11_SXISU_ARNS_Pos                  (5UL)
#define R_SYSC_SYS_MSTACCCTL12_SXDSI_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL12_SXDSI_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL12_SXDSI_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL12_SXDSI_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL12_SXDSI_AWSEL_Msk                 (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL12_SXDSI_AWSEL_Pos                 (3UL)
#define R_SYSC_SYS_MSTACCCTL12_SXDSI_ARPU_Msk                  (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL12_SXDSI_ARPU_Pos                  (4UL)
#define R_SYSC_SYS_MSTACCCTL12_SXDSI_ARNS_Msk                  (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL12_SXDSI_ARNS_Pos                  (5UL)
#define R_SYSC_SYS_MSTACCCTL12_SXDSI_ARSEL_Msk                 (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL12_SXDSI_ARSEL_Pos                 (7UL)
#define R_SYSC_SYS_MSTACCCTL13_SXLCD_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL13_SXLCD_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL13_SXLCD_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL13_SXLCD_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL13_SXLCD_AWSEL_Msk                 (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL13_SXLCD_AWSEL_Pos                 (3UL)
#define R_SYSC_SYS_MSTACCCTL13_SXLCD_ARPU_Msk                  (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL13_SXLCD_ARPU_Pos                  (4UL)
#define R_SYSC_SYS_MSTACCCTL13_SXLCD_ARNS_Msk                  (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL13_SXLCD_ARNS_Pos                  (5UL)
#define R_SYSC_SYS_MSTACCCTL13_SXLCD_ARSEL_Msk                 (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL13_SXLCD_ARSEL_Pos                 (7UL)
#define R_SYSC_SYS_MSTACCCTL14_SXGPU_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL14_SXGPU_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL14_SXGPU_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL14_SXGPU_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL14_SXGPU_AWSEL_Msk                 (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL14_SXGPU_AWSEL_Pos                 (3UL)
#define R_SYSC_SYS_MSTACCCTL14_SXGPU_ARPU_Msk                  (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL14_SXGPU_ARPU_Pos                  (4UL)
#define R_SYSC_SYS_MSTACCCTL14_SXGPU_ARNS_Msk                  (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL14_SXGPU_ARNS_Pos                  (5UL)
#define R_SYSC_SYS_MSTACCCTL14_SXGPU_ARSEL_Msk                 (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL14_SXGPU_ARSEL_Pos                 (7UL)
#define R_SYSC_SYS_MSTACCCTL15_SXVCP_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL15_SXVCP_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL15_SXVCP_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL15_SXVCP_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL15_SXVCP_AWSEL_Msk                 (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL15_SXVCP_AWSEL_Pos                 (3UL)
#define R_SYSC_SYS_MSTACCCTL15_SXVCP_ARPU_Msk                  (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL15_SXVCP_ARPU_Pos                  (4UL)
#define R_SYSC_SYS_MSTACCCTL15_SXVCP_ARNS_Msk                  (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL15_SXVCP_ARNS_Pos                  (5UL)
#define R_SYSC_SYS_MSTACCCTL15_SXVCP_ARSEL_Msk                 (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL15_SXVCP_ARSEL_Pos                 (7UL)
#define R_SYSC_SYS_MSTACCCTL16_SXDRP_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL16_SXDRP_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL16_SXDRP_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL16_SXDRP_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL16_SXDRP_AWSEL_Msk                 (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL16_SXDRP_AWSEL_Pos                 (3UL)
#define R_SYSC_SYS_MSTACCCTL16_SXDRP_ARPU_Msk                  (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL16_SXDRP_ARPU_Pos                  (4UL)
#define R_SYSC_SYS_MSTACCCTL16_SXDRP_ARNS_Msk                  (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL16_SXDRP_ARNS_Pos                  (5UL)
#define R_SYSC_SYS_MSTACCCTL16_SXDRP_ARSEL_Msk                 (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL16_SXDRP_ARSEL_Pos                 (7UL)
#define R_SYSC_SYS_MSTACCCTL17_SXDRA_AWPU_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL17_SXDRA_AWPU_Pos                  (0UL)
#define R_SYSC_SYS_MSTACCCTL17_SXDRA_AWNS_Msk                  (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL17_SXDRA_AWNS_Pos                  (1UL)
#define R_SYSC_SYS_MSTACCCTL17_SXDRA_AWSEL_Msk                 (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL17_SXDRA_AWSEL_Pos                 (3UL)
#define R_SYSC_SYS_MSTACCCTL17_SXDRA_ARPU_Msk                  (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL17_SXDRA_ARPU_Pos                  (4UL)
#define R_SYSC_SYS_MSTACCCTL17_SXDRA_ARNS_Msk                  (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL17_SXDRA_ARNS_Pos                  (5UL)
#define R_SYSC_SYS_MSTACCCTL17_SXDRA_ARSEL_Msk                 (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL17_SXDRA_ARSEL_Pos                 (7UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM0_AWPU_Msk                 (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM0_AWPU_Pos                 (0UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM0_AWNS_Msk                 (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM0_AWNS_Pos                 (1UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM0_AWSEL_Msk                (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM0_AWSEL_Pos                (3UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM0_ARPU_Msk                 (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM0_ARPU_Pos                 (4UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM0_ARNS_Msk                 (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM0_ARNS_Pos                 (5UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM0_ARSEL_Msk                (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM0_ARSEL_Pos                (7UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM1_AWPU_Msk                 (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM1_AWPU_Pos                 (8UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM1_AWNS_Msk                 (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM1_AWNS_Pos                 (9UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM1_AWSEL_Msk                (0x00000800UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM1_AWSEL_Pos                (11UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM1_ARPU_Msk                 (0x00001000UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM1_ARPU_Pos                 (12UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM1_ARNS_Msk                 (0x00002000UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM1_ARNS_Pos                 (13UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM1_ARSEL_Msk                (0x00008000UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRM1_ARSEL_Pos                (15UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRW0_ARPU_Msk                 (0x00100000UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRW0_ARPU_Pos                 (20UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRW0_ARNS_Msk                 (0x00200000UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRW0_ARNS_Pos                 (21UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRW0_ARSEL_Msk                (0x00800000UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRW0_ARSEL_Pos                (23UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRW1_ARPU_Msk                 (0x10000000UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRW1_ARPU_Pos                 (28UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRW1_ARNS_Msk                 (0x20000000UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRW1_ARNS_Pos                 (29UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRW1_ARSEL_Msk                (0x80000000UL)
#define R_SYSC_SYS_MSTACCCTL18_SXDRW1_ARSEL_Pos                (31UL)
#define R_SYSC_SYS_SLVACCCTL0_MPCPG_SL_Msk                     (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL0_MPCPG_SL_Pos                     (0UL)
#define R_SYSC_SYS_SLVACCCTL1_MPSYS_SL_Msk                     (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL1_MPSYS_SL_Pos                     (0UL)
#define R_SYSC_SYS_SLVACCCTL2_MPICU0_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL2_MPICU0_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL2_MPICU1_SL_Msk                    (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL2_MPICU1_SL_Pos                    (2UL)
#define R_SYSC_SYS_SLVACCCTL3_MXMDMC_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL3_MXMDMC_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL4_MPMSRM0_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL4_MPMSRM0_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL4_MPMSRM1_SL_Msk                   (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL4_MPMSRM1_SL_Pos                   (2UL)
#define R_SYSC_SYS_SLVACCCTL5_MPCST_SL_Msk                     (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL5_MPCST_SL_Pos                     (0UL)
#define R_SYSC_SYS_SLVACCCTL6_MPMHU_SL_Msk                     (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL6_MPMHU_SL_Pos                     (0UL)
#define R_SYSC_SYS_SLVACCCTL7_MOMCMT0_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL7_MOMCMT0_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL7_MOMCMT1_SL_Msk                   (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL7_MOMCMT1_SL_Pos                   (2UL)
#define R_SYSC_SYS_SLVACCCTL7_MOMCMT2_SL_Msk                   (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL7_MOMCMT2_SL_Pos                   (4UL)
#define R_SYSC_SYS_SLVACCCTL7_MOMCMT3_SL_Msk                   (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL7_MOMCMT3_SL_Pos                   (6UL)
#define R_SYSC_SYS_SLVACCCTL7_MPMOST0_SL_Msk                   (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL7_MPMOST0_SL_Pos                   (8UL)
#define R_SYSC_SYS_SLVACCCTL7_MPMOST1_SL_Msk                   (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL7_MPMOST1_SL_Pos                   (10UL)
#define R_SYSC_SYS_SLVACCCTL8_MOMWDT_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL8_MOMWDT_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL9_MORTC_SL_Msk                     (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL9_MORTC_SL_Pos                     (0UL)
#define R_SYSC_SYS_SLVACCCTL10_MORTR_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL10_MORTR_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL11_SPI_REG_SL_Msk                  (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL11_SPI_REG_SL_Pos                  (0UL)
#define R_SYSC_SYS_SLVACCCTL12_MHGPO_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL12_MHGPO_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL13_MPPDM0_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL13_MPPDM0_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL13_MPPDM1_SL_Msk                   (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL13_MPPDM1_SL_Pos                   (2UL)
#define R_SYSC_SYS_SLVACCCTL14_MOADC_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL14_MOADC_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL15_MPMTSU0_SL_Msk                  (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL15_MPMTSU0_SL_Pos                  (0UL)
#define R_SYSC_SYS_SLVACCCTL17_MPCMA_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL17_MPCMA_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL17_MPCMO_SL_Msk                    (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL17_MPCMO_SL_Pos                    (2UL)
#define R_SYSC_SYS_SLVACCCTL19_MOSCF_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL19_MOSCF_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL20_MOMI2C_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL20_MOMI2C_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL21_MPTSPI_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL21_MPTSPI_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL21_MPTM33_SL_Msk                   (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL21_MPTM33_SL_Pos                   (2UL)
#define R_SYSC_SYS_SLVACCCTL22_MXMGPV_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL22_MXMGPV_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL22_MCPU_SYS_GPV_SL_Msk             (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL22_MCPU_SYS_GPV_SL_Pos             (2UL)
#define R_SYSC_SYS_SLVACCCTL22_MCPU_PERI0_GPV_SL_Msk           (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL22_MCPU_PERI0_GPV_SL_Pos           (4UL)
#define R_SYSC_SYS_SLVACCCTL22_MCPU_PERI1_GPV_SL_Msk           (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL22_MCPU_PERI1_GPV_SL_Pos           (6UL)
#define R_SYSC_SYS_SLVACCCTL22_MCPU_PERI2_GPV_SL_Msk           (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL22_MCPU_PERI2_GPV_SL_Pos           (8UL)
#define R_SYSC_SYS_SLVACCCTL32_MXADMC0_SL_Msk                  (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL32_MXADMC0_SL_Pos                  (0UL)
#define R_SYSC_SYS_SLVACCCTL32_MXADMC1_SL_Msk                  (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL32_MXADMC1_SL_Pos                  (2UL)
#define R_SYSC_SYS_SLVACCCTL33_MPASRM_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL33_MPASRM_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM0_SL_Msk                  (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM0_SL_Pos                  (6UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM1_SL_Msk                  (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM1_SL_Pos                  (8UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM2_SL_Msk                  (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM2_SL_Pos                  (10UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM3_SL_Msk                  (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM3_SL_Pos                  (12UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM4_SL_Msk                  (0x0000C000UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM4_SL_Pos                  (14UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM5_SL_Msk                  (0x00030000UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM5_SL_Pos                  (16UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM6_SL_Msk                  (0x000C0000UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM6_SL_Pos                  (18UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM7_SL_Msk                  (0x00300000UL)
#define R_SYSC_SYS_SLVACCCTL33_MPDSRM7_SL_Pos                  (20UL)
#define R_SYSC_SYS_SLVACCCTL35_MPSYC_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL35_MPSYC_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL36_MPAOST0_SL_Msk                  (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL36_MPAOST0_SL_Pos                  (0UL)
#define R_SYSC_SYS_SLVACCCTL36_MPAOST1_SL_Msk                  (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL36_MPAOST1_SL_Pos                  (2UL)
#define R_SYSC_SYS_SLVACCCTL37_MOAWDT_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL37_MOAWDT_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C0_SL_Msk                  (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C0_SL_Pos                  (0UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C1_SL_Msk                  (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C1_SL_Pos                  (2UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C2_SL_Msk                  (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C2_SL_Pos                  (4UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C3_SL_Msk                  (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C3_SL_Pos                  (6UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C4_SL_Msk                  (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C4_SL_Pos                  (8UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C5_SL_Msk                  (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C5_SL_Pos                  (10UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C6_SL_Msk                  (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C6_SL_Pos                  (12UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C7_SL_Msk                  (0x0000C000UL)
#define R_SYSC_SYS_SLVACCCTL38_MOAI2C7_SL_Pos                  (14UL)
#define R_SYSC_SYS_SLVACCCTL39_MXSD0_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL39_MXSD0_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL39_MXSD1_SL_Msk                    (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL39_MXSD1_SL_Pos                    (2UL)
#define R_SYSC_SYS_SLVACCCTL39_MXSD2_SL_Msk                    (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL39_MXSD2_SL_Pos                    (4UL)
#define R_SYSC_SYS_SLVACCCTL40_MXU3H0_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL40_MXU3H0_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL40_MXU3H1_SL_Msk                   (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL40_MXU3H1_SL_Pos                   (2UL)
#define R_SYSC_SYS_SLVACCCTL40_MPU3P0_SL_Msk                   (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL40_MPU3P0_SL_Pos                   (4UL)
#define R_SYSC_SYS_SLVACCCTL40_MPU3P1_SL_Msk                   (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL40_MPU3P1_SL_Pos                   (6UL)
#define R_SYSC_SYS_SLVACCCTL40_MHU2H0_SL_Msk                   (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL40_MHU2H0_SL_Pos                   (8UL)
#define R_SYSC_SYS_SLVACCCTL40_MHU2H1_SL_Msk                   (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL40_MHU2H1_SL_Pos                   (10UL)
#define R_SYSC_SYS_SLVACCCTL40_MPU2P0_SL_Msk                   (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL40_MPU2P0_SL_Pos                   (12UL)
#define R_SYSC_SYS_SLVACCCTL40_MPU2P1_SL_Msk                   (0x0000C000UL)
#define R_SYSC_SYS_SLVACCCTL40_MPU2P1_SL_Pos                   (14UL)
#define R_SYSC_SYS_SLVACCCTL41_MXGBE0_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL41_MXGBE0_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL41_MXGBE1_SL_Msk                   (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL41_MXGBE1_SL_Pos                   (2UL)
#define R_SYSC_SYS_SLVACCCTL43_MPDDM0_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL43_MPDDM0_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL43_MPDDM1_SL_Msk                   (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL43_MPDDM1_SL_Pos                   (2UL)
#define R_SYSC_SYS_SLVACCCTL43_MPDDP0_SL_Msk                   (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL43_MPDDP0_SL_Pos                   (4UL)
#define R_SYSC_SYS_SLVACCCTL43_MPDDP1_SL_Msk                   (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL43_MPDDP1_SL_Pos                   (6UL)
#define R_SYSC_SYS_SLVACCCTL44_MPCRU0_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL44_MPCRU0_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL44_MPCRU1_SL_Msk                   (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL44_MPCRU1_SL_Pos                   (2UL)
#define R_SYSC_SYS_SLVACCCTL44_MPCRU2_SL_Msk                   (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL44_MPCRU2_SL_Pos                   (4UL)
#define R_SYSC_SYS_SLVACCCTL44_MPCRU3_SL_Msk                   (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL44_MPCRU3_SL_Pos                   (6UL)
#define R_SYSC_SYS_SLVACCCTL45_MPISP_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL45_MPISP_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL45_MXISP_SL_Msk                    (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL45_MXISP_SL_Pos                    (2UL)
#define R_SYSC_SYS_SLVACCCTL46_MPISU_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL46_MPISU_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL47_MPDSD_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL47_MPDSD_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL47_MPDSL_SL_Msk                    (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL47_MPDSL_SL_Pos                    (2UL)
#define R_SYSC_SYS_SLVACCCTL48_MPLCD_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL48_MPLCD_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL49_MXGPU_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL49_MXGPU_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL50_MPVCC_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL50_MPVCC_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL51_MPSSIU_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL51_MPSSIU_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL51_MPSSIUDMC_SL_Msk                (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL51_MPSSIUDMC_SL_Pos                (2UL)
#define R_SYSC_SYS_SLVACCCTL51_MPADMC_SL_Msk                   (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL51_MPADMC_SL_Pos                   (4UL)
#define R_SYSC_SYS_SLVACCCTL52_MOSPD0_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL52_MOSPD0_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL52_MOSPD1_SL_Msk                   (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL52_MOSPD1_SL_Pos                   (2UL)
#define R_SYSC_SYS_SLVACCCTL52_MOSPD2_SL_Msk                   (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL52_MOSPD2_SL_Pos                   (4UL)
#define R_SYSC_SYS_SLVACCCTL53_MPSCU_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL53_MPSCU_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL53_MPSCUDMC_SL_Msk                 (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL53_MPSCUDMC_SL_Pos                 (2UL)
#define R_SYSC_SYS_SLVACCCTL53_MPADG_SL_Msk                    (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL53_MPADG_SL_Pos                    (4UL)
#define R_SYSC_SYS_SLVACCCTL54_MXDRP_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL54_MXDRP_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL54_MXDRA_SL_Msk                    (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL54_MXDRA_SL_Pos                    (2UL)
#define R_SYSC_SYS_SLVACCCTL54_MXDRS_SL_Msk                    (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL54_MXDRS_SL_Pos                    (4UL)
#define R_SYSC_SYS_SLVACCCTL55_MXGIC_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL55_MXGIC_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL56_MPMTSU1_SL_Msk                  (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL56_MPMTSU1_SL_Pos                  (0UL)
#define R_SYSC_SYS_SLVACCCTL57_MPTA55_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL57_MPTA55_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL57_MPTR8_SL_Msk                    (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL57_MPTR8_SL_Pos                    (2UL)
#define R_SYSC_SYS_SLVACCCTL57_MPTDD00_SL_Msk                  (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL57_MPTDD00_SL_Pos                  (4UL)
#define R_SYSC_SYS_SLVACCCTL57_MPTDD01_SL_Msk                  (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL57_MPTDD01_SL_Pos                  (6UL)
#define R_SYSC_SYS_SLVACCCTL57_MPTDD10_SL_Msk                  (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL57_MPTDD10_SL_Pos                  (8UL)
#define R_SYSC_SYS_SLVACCCTL57_MPTDD11_SL_Msk                  (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL57_MPTDD11_SL_Pos                  (10UL)
#define R_SYSC_SYS_SLVACCCTL57_MPTPCI_SL_Msk                   (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL57_MPTPCI_SL_Pos                   (12UL)
#define R_SYSC_SYS_SLVACCCTL58_MXV0GPV_SL_Msk                  (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL58_MXV0GPV_SL_Pos                  (0UL)
#define R_SYSC_SYS_SLVACCCTL58_MXV1GPV_SL_Msk                  (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL58_MXV1GPV_SL_Pos                  (2UL)
#define R_SYSC_SYS_SLVACCCTL58_MXDPGPV_SL_Msk                  (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL58_MXDPGPV_SL_Pos                  (4UL)
#define R_SYSC_SYS_SLVACCCTL58_MXCMGPV_SL_Msk                  (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL58_MXCMGPV_SL_Pos                  (6UL)
#define R_SYSC_SYS_SLVACCCTL58_MXACGPV_SL_Msk                  (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL58_MXACGPV_SL_Pos                  (8UL)
#define R_SYSC_SYS_SLVACCCTL58_ACPU_PERI0_GPV_SL_Msk           (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL58_ACPU_PERI0_GPV_SL_Pos           (10UL)
#define R_SYSC_SYS_SLVACCCTL58_ACPU_PERI1_GPV_SL_Msk           (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL58_ACPU_PERI1_GPV_SL_Pos           (12UL)
#define R_SYSC_SYS_SLVACCCTL58_MXACR0GPV_SL_Msk                (0x0000C000UL)
#define R_SYSC_SYS_SLVACCCTL58_MXACR0GPV_SL_Pos                (14UL)
#define R_SYSC_SYS_SLVACCCTL58_MXACR1GPV_SL_Msk                (0x00030000UL)
#define R_SYSC_SYS_SLVACCCTL58_MXACR1GPV_SL_Pos                (16UL)
#define R_SYSC_SYS_SLVACCCTL58_ACPU_REG2_GPV_SL_Msk            (0x000C0000UL)
#define R_SYSC_SYS_SLVACCCTL58_ACPU_REG2_GPV_SL_Pos            (18UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERIVIDEO0_GPV_SL_Msk      (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERIVIDEO0_GPV_SL_Pos      (0UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERIVIDEO1_GPV_SL_Msk      (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERIVIDEO1_GPV_SL_Pos      (2UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERIDRP0_GPV_SL_Msk        (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERIDRP0_GPV_SL_Pos        (4UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERIDRP1_GPV_SL_Msk        (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERIDRP1_GPV_SL_Pos        (6UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERICOM0_GPV_SL_Msk        (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERICOM0_GPV_SL_Pos        (8UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERICOM1_GPV_SL_Msk        (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERICOM1_GPV_SL_Pos        (10UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERIDDR_GPV_SL_Msk         (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERIDDR_GPV_SL_Pos         (12UL)
#define R_SYSC_SYS_SLVACCCTL59_MXCMSGPV_SL_Msk                 (0x0000C000UL)
#define R_SYSC_SYS_SLVACCCTL59_MXCMSGPV_SL_Pos                 (14UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERICOM2_GPV_SL_Msk        (0x00030000UL)
#define R_SYSC_SYS_SLVACCCTL59_ACPU_PERICOM2_GPV_SL_Pos        (16UL)
#define R_SYSC_SYS_SLVACCCTL64_MOCRC_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL64_MOCRC_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL65_MOGPT0_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL65_MOGPT0_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL65_MOGPT1_SL_Msk                   (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL65_MOGPT1_SL_Pos                   (2UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE0_SL_Msk                   (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE0_SL_Pos                   (0UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE1_SL_Msk                   (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE1_SL_Pos                   (2UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE2_SL_Msk                   (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE2_SL_Pos                   (4UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE3_SL_Msk                   (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE3_SL_Pos                   (6UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE4_SL_Msk                   (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE4_SL_Pos                   (8UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE5_SL_Msk                   (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE5_SL_Pos                   (10UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE6_SL_Msk                   (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE6_SL_Pos                   (12UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE7_SL_Msk                   (0x0000C000UL)
#define R_SYSC_SYS_SLVACCCTL66_MOPOE7_SL_Pos                   (14UL)
#define R_SYSC_SYS_SLVACCCTL67_MORCMT0_SL_Msk                  (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL67_MORCMT0_SL_Pos                  (0UL)
#define R_SYSC_SYS_SLVACCCTL67_MORCMT1_SL_Msk                  (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL67_MORCMT1_SL_Pos                  (2UL)
#define R_SYSC_SYS_SLVACCCTL67_MORCMT2_SL_Msk                  (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL67_MORCMT2_SL_Pos                  (4UL)
#define R_SYSC_SYS_SLVACCCTL67_MORCMT3_SL_Msk                  (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL67_MORCMT3_SL_Pos                  (6UL)
#define R_SYSC_SYS_SLVACCCTL68_MORWDT0_SL_Msk                  (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL68_MORWDT0_SL_Pos                  (0UL)
#define R_SYSC_SYS_SLVACCCTL68_MORWDT1_SL_Msk                  (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL68_MORWDT1_SL_Pos                  (2UL)
#define R_SYSC_SYS_SLVACCCTL80_I3C_SL_Msk                      (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL80_I3C_SL_Pos                      (0UL)
#define R_SYSC_SYS_SLVACCCTL81_CANFD_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL81_CANFD_SL_Pos                    (0UL)
#define R_SYSC_SYS_SLVACCCTL82_RCPU_SRAM_SL_Msk                (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL82_RCPU_SRAM_SL_Pos                (0UL)
#define R_SYSC_SYS_SLVACCCTL88_RCPU_SL_Msk                     (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL88_RCPU_SL_Pos                     (0UL)
#define R_SYSC_SYS_SLVACCCTL89_MCPU_SL_Msk                     (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL89_MCPU_SL_Pos                     (0UL)
#define R_SYSC_SYS_SLVACCCTL91_LSI_SL_Msk                      (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL91_LSI_SL_Pos                      (0UL)
#define R_SYSC_SYS_SLVACCCTL92_AOF_SL_Msk                      (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL92_AOF_SL_Pos                      (0UL)
#define R_SYSC_SYS_SLVACCCTL93_GPREG_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL93_GPREG_SL_Pos                    (0UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_BOOT_Msk                   (0x00000007UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_BOOT_Pos                   (0UL)
#define R_SYSC_SYS_LSI_MODE_STAT_DEBUGEN_Msk                   (0x00000200UL)
#define R_SYSC_SYS_LSI_MODE_STAT_DEBUGEN_Pos                   (9UL)
#define R_SYSC_SYS_LSI_MODE_STAT_BOOTSELECTER_Msk              (0x00000400UL)
#define R_SYSC_SYS_LSI_MODE_STAT_BOOTSELECTER_Pos              (10UL)
#define R_SYSC_SYS_LSI_MODE_STAT_BOOTPLLCA55_Msk               (0x00001800UL)
#define R_SYSC_SYS_LSI_MODE_STAT_BOOTPLLCA55_Pos               (11UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_CLKS_Msk                   (0x00002000UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_CLKS_Pos                   (13UL)
#define R_SYSC_SYS_LSI_DEVID_DEV_ID_Msk                        (0xFFFFFFFFUL)
#define R_SYSC_SYS_LSI_DEVID_DEV_ID_Pos                        (0UL)
#define R_SYSC_SYS_LSI_PRR_GPU_DIS_Msk                         (0x00000001UL)
#define R_SYSC_SYS_LSI_PRR_GPU_DIS_Pos                         (0UL)
#define R_SYSC_SYS_LSI_PRR_ISP_DIS_Msk                         (0x00000010UL)
#define R_SYSC_SYS_LSI_PRR_ISP_DIS_Pos                         (4UL)
#define R_SYSC_SYS_LSI_OTPTSU0TRMVAL0_TSU0_TRMVAL0_Msk         (0xFFFFFFFFUL)
#define R_SYSC_SYS_LSI_OTPTSU0TRMVAL0_TSU0_TRMVAL0_Pos         (0UL)
#define R_SYSC_SYS_LSI_OTPTSU0TRMVAL1_TSU0_TRMVAL1_Msk         (0xFFFFFFFFUL)
#define R_SYSC_SYS_LSI_OTPTSU0TRMVAL1_TSU0_TRMVAL1_Pos         (0UL)
#define R_SYSC_SYS_LSI_OTPTSU1TRMVAL0_TSU1_TRMVAL0_Msk         (0xFFFFFFFFUL)
#define R_SYSC_SYS_LSI_OTPTSU1TRMVAL0_TSU1_TRMVAL0_Pos         (0UL)
#define R_SYSC_SYS_LSI_OTPTSU1TRMVAL1_TSU1_TRMVAL1_Msk         (0xFFFFFFFFUL)
#define R_SYSC_SYS_LSI_OTPTSU1TRMVAL1_TSU1_TRMVAL1_Pos         (0UL)
#define R_SYSC_SYS_AOF0_OFS00_0_Msk                            (0x0000003FUL)
#define R_SYSC_SYS_AOF0_OFS00_0_Pos                            (0UL)
#define R_SYSC_SYS_AOF0_OFS01_0_Msk                            (0x00003F00UL)
#define R_SYSC_SYS_AOF0_OFS01_0_Pos                            (8UL)
#define R_SYSC_SYS_AOF0_OFS10_0_Msk                            (0x003F0000UL)
#define R_SYSC_SYS_AOF0_OFS10_0_Pos                            (16UL)
#define R_SYSC_SYS_AOF0_OFS11_0_Msk                            (0x3F000000UL)
#define R_SYSC_SYS_AOF0_OFS11_0_Pos                            (24UL)
#define R_SYSC_SYS_AOF1_OFS00_1_Msk                            (0x0000003FUL)
#define R_SYSC_SYS_AOF1_OFS00_1_Pos                            (0UL)
#define R_SYSC_SYS_AOF1_OFS01_1_Msk                            (0x00003F00UL)
#define R_SYSC_SYS_AOF1_OFS01_1_Pos                            (8UL)
#define R_SYSC_SYS_AOF1_OFS10_1_Msk                            (0x003F0000UL)
#define R_SYSC_SYS_AOF1_OFS10_1_Pos                            (16UL)
#define R_SYSC_SYS_AOF1_OFS11_1_Msk                            (0x3F000000UL)
#define R_SYSC_SYS_AOF1_OFS11_1_Pos                            (24UL)
#define R_SYSC_SYS_AOF2_OFS00_2_Msk                            (0x0000003FUL)
#define R_SYSC_SYS_AOF2_OFS00_2_Pos                            (0UL)
#define R_SYSC_SYS_AOF2_OFS01_2_Msk                            (0x00003F00UL)
#define R_SYSC_SYS_AOF2_OFS01_2_Pos                            (8UL)
#define R_SYSC_SYS_AOF2_OFS10_2_Msk                            (0x003F0000UL)
#define R_SYSC_SYS_AOF2_OFS10_2_Pos                            (16UL)
#define R_SYSC_SYS_AOF2_OFS11_2_Msk                            (0x3F000000UL)
#define R_SYSC_SYS_AOF2_OFS11_2_Pos                            (24UL)
#define R_SYSC_SYS_AOF3_OFS00_3_Msk                            (0x0000003FUL)
#define R_SYSC_SYS_AOF3_OFS00_3_Pos                            (0UL)
#define R_SYSC_SYS_AOF3_OFS01_3_Msk                            (0x00003F00UL)
#define R_SYSC_SYS_AOF3_OFS01_3_Pos                            (8UL)
#define R_SYSC_SYS_AOF3_OFS10_3_Msk                            (0x003F0000UL)
#define R_SYSC_SYS_AOF3_OFS10_3_Pos                            (16UL)
#define R_SYSC_SYS_AOF3_OFS11_3_Msk                            (0x3F000000UL)
#define R_SYSC_SYS_AOF3_OFS11_3_Pos                            (24UL)
#define R_SYSC_SYS_AOF4_OFS00_4_Msk                            (0x0000003FUL)
#define R_SYSC_SYS_AOF4_OFS00_4_Pos                            (0UL)
#define R_SYSC_SYS_AOF4_OFS01_4_Msk                            (0x00003F00UL)
#define R_SYSC_SYS_AOF4_OFS01_4_Pos                            (8UL)
#define R_SYSC_SYS_AOF4_OFS10_4_Msk                            (0x003F0000UL)
#define R_SYSC_SYS_AOF4_OFS10_4_Pos                            (16UL)
#define R_SYSC_SYS_AOF4_OFS11_4_Msk                            (0x3F000000UL)
#define R_SYSC_SYS_AOF4_OFS11_4_Pos                            (24UL)
#define R_SYSC_SYS_AOF16_OFS00_16_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF16_OFS00_16_Pos                          (0UL)
#define R_SYSC_SYS_AOF16_OFS01_16_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF16_OFS01_16_Pos                          (8UL)
#define R_SYSC_SYS_AOF16_OFS10_16_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF16_OFS10_16_Pos                          (16UL)
#define R_SYSC_SYS_AOF16_OFS11_16_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF16_OFS11_16_Pos                          (24UL)
#define R_SYSC_SYS_AOF17_OFS00_17_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF17_OFS00_17_Pos                          (0UL)
#define R_SYSC_SYS_AOF17_OFS01_17_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF17_OFS01_17_Pos                          (8UL)
#define R_SYSC_SYS_AOF17_OFS10_17_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF17_OFS10_17_Pos                          (16UL)
#define R_SYSC_SYS_AOF17_OFS11_17_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF17_OFS11_17_Pos                          (24UL)
#define R_SYSC_SYS_AOF18_OFS00_18_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF18_OFS00_18_Pos                          (0UL)
#define R_SYSC_SYS_AOF18_OFS01_18_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF18_OFS01_18_Pos                          (8UL)
#define R_SYSC_SYS_AOF18_OFS10_18_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF18_OFS10_18_Pos                          (16UL)
#define R_SYSC_SYS_AOF18_OFS11_18_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF18_OFS11_18_Pos                          (24UL)
#define R_SYSC_SYS_AOF19_OFS00_19_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF19_OFS00_19_Pos                          (0UL)
#define R_SYSC_SYS_AOF19_OFS01_19_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF19_OFS01_19_Pos                          (8UL)
#define R_SYSC_SYS_AOF19_OFS10_19_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF19_OFS10_19_Pos                          (16UL)
#define R_SYSC_SYS_AOF19_OFS11_19_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF19_OFS11_19_Pos                          (24UL)
#define R_SYSC_SYS_AOF20_OFS00_20_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF20_OFS00_20_Pos                          (0UL)
#define R_SYSC_SYS_AOF20_OFS01_20_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF20_OFS01_20_Pos                          (8UL)
#define R_SYSC_SYS_AOF20_OFS10_20_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF20_OFS10_20_Pos                          (16UL)
#define R_SYSC_SYS_AOF20_OFS11_20_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF20_OFS11_20_Pos                          (24UL)
#define R_SYSC_SYS_AOF21_OFS00_21_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF21_OFS00_21_Pos                          (0UL)
#define R_SYSC_SYS_AOF21_OFS01_21_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF21_OFS01_21_Pos                          (8UL)
#define R_SYSC_SYS_AOF21_OFS10_21_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF21_OFS10_21_Pos                          (16UL)
#define R_SYSC_SYS_AOF21_OFS11_21_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF21_OFS11_21_Pos                          (24UL)
#define R_SYSC_SYS_AOF22_OFS00_22_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF22_OFS00_22_Pos                          (0UL)
#define R_SYSC_SYS_AOF22_OFS01_22_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF22_OFS01_22_Pos                          (8UL)
#define R_SYSC_SYS_AOF22_OFS10_22_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF22_OFS10_22_Pos                          (16UL)
#define R_SYSC_SYS_AOF22_OFS11_22_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF22_OFS11_22_Pos                          (24UL)
#define R_SYSC_SYS_AOF23_OFS00_23_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF23_OFS00_23_Pos                          (0UL)
#define R_SYSC_SYS_AOF23_OFS01_23_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF23_OFS01_23_Pos                          (8UL)
#define R_SYSC_SYS_AOF23_OFS10_23_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF23_OFS10_23_Pos                          (16UL)
#define R_SYSC_SYS_AOF23_OFS11_23_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF23_OFS11_23_Pos                          (24UL)
#define R_SYSC_SYS_AOF24_OFS00_24_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF24_OFS00_24_Pos                          (0UL)
#define R_SYSC_SYS_AOF24_OFS01_24_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF24_OFS01_24_Pos                          (8UL)
#define R_SYSC_SYS_AOF24_OFS10_24_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF24_OFS10_24_Pos                          (16UL)
#define R_SYSC_SYS_AOF24_OFS11_24_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF24_OFS11_24_Pos                          (24UL)
#define R_SYSC_SYS_AOF25_OFS00_25_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF25_OFS00_25_Pos                          (0UL)
#define R_SYSC_SYS_AOF25_OFS01_25_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF25_OFS01_25_Pos                          (8UL)
#define R_SYSC_SYS_AOF25_OFS10_25_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF25_OFS10_25_Pos                          (16UL)
#define R_SYSC_SYS_AOF25_OFS11_25_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF25_OFS11_25_Pos                          (24UL)
#define R_SYSC_SYS_AOF32_OFS0011_MCPUS_Msk                     (0x000000FFUL)
#define R_SYSC_SYS_AOF32_OFS0011_MCPUS_Pos                     (0UL)
#define R_SYSC_SYS_AOF32_OFS0100_MCPUS_Msk                     (0x0000FF00UL)
#define R_SYSC_SYS_AOF32_OFS0100_MCPUS_Pos                     (8UL)
#define R_SYSC_SYS_AOF33_OFS00_33_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF33_OFS00_33_Pos                          (0UL)
#define R_SYSC_SYS_AOF33_OFS01_33_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF33_OFS01_33_Pos                          (8UL)
#define R_SYSC_SYS_AOF33_OFS10_33_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF33_OFS10_33_Pos                          (16UL)
#define R_SYSC_SYS_AOF33_OFS11_33_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF33_OFS11_33_Pos                          (24UL)
#define R_SYSC_SYS_AOF40_OFS00_40_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF40_OFS00_40_Pos                          (0UL)
#define R_SYSC_SYS_AOF40_OFS01_40_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF40_OFS01_40_Pos                          (8UL)
#define R_SYSC_SYS_AOF40_OFS10_40_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF40_OFS10_40_Pos                          (16UL)
#define R_SYSC_SYS_AOF40_OFS11_40_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF40_OFS11_40_Pos                          (24UL)
#define R_SYSC_SYS_AOF41_OFS00_41_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF41_OFS00_41_Pos                          (0UL)
#define R_SYSC_SYS_AOF41_OFS01_41_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF41_OFS01_41_Pos                          (8UL)
#define R_SYSC_SYS_AOF41_OFS10_41_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF41_OFS10_41_Pos                          (16UL)
#define R_SYSC_SYS_AOF41_OFS11_41_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF41_OFS11_41_Pos                          (24UL)
#define R_SYSC_SYS_AOF42_OFS00_42_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF42_OFS00_42_Pos                          (0UL)
#define R_SYSC_SYS_AOF42_OFS01_42_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF42_OFS01_42_Pos                          (8UL)
#define R_SYSC_SYS_AOF42_OFS10_42_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF42_OFS10_42_Pos                          (16UL)
#define R_SYSC_SYS_AOF42_OFS11_42_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF42_OFS11_42_Pos                          (24UL)
#define R_SYSC_SYS_AOF43_OFS00_43_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF43_OFS00_43_Pos                          (0UL)
#define R_SYSC_SYS_AOF43_OFS01_43_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF43_OFS01_43_Pos                          (8UL)
#define R_SYSC_SYS_AOF43_OFS10_43_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF43_OFS10_43_Pos                          (16UL)
#define R_SYSC_SYS_AOF43_OFS11_43_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF43_OFS11_43_Pos                          (24UL)
#define R_SYSC_SYS_AOF48_OFS00_48_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF48_OFS00_48_Pos                          (0UL)
#define R_SYSC_SYS_AOF48_OFS01_48_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF48_OFS01_48_Pos                          (8UL)
#define R_SYSC_SYS_AOF48_OFS10_48_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF48_OFS10_48_Pos                          (16UL)
#define R_SYSC_SYS_AOF48_OFS11_48_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF48_OFS11_48_Pos                          (24UL)
#define R_SYSC_SYS_AOF49_OFS00_49_Msk                          (0x0000003FUL)
#define R_SYSC_SYS_AOF49_OFS00_49_Pos                          (0UL)
#define R_SYSC_SYS_AOF49_OFS01_49_Msk                          (0x00003F00UL)
#define R_SYSC_SYS_AOF49_OFS01_49_Pos                          (8UL)
#define R_SYSC_SYS_AOF49_OFS10_49_Msk                          (0x003F0000UL)
#define R_SYSC_SYS_AOF49_OFS10_49_Pos                          (16UL)
#define R_SYSC_SYS_AOF49_OFS11_49_Msk                          (0x3F000000UL)
#define R_SYSC_SYS_AOF49_OFS11_49_Pos                          (24UL)
#define R_SYSC_SYS_ACPU_CFG_SMPL_ASTARTMPL_Msk                 (0x000000FFUL)
#define R_SYSC_SYS_ACPU_CFG_SMPL_ASTARTMPL_Pos                 (0UL)
#define R_SYSC_SYS_ACPU_CFG_SMPH_ASTARTMPH_Msk                 (0xFFF00000UL)
#define R_SYSC_SYS_ACPU_CFG_SMPH_ASTARTMPH_Pos                 (20UL)
#define R_SYSC_SYS_ACPU_CFG_EMPL_AENDMPLMPL_Msk                (0xFFF00000UL)
#define R_SYSC_SYS_ACPU_CFG_EMPL_AENDMPLMPL_Pos                (20UL)
#define R_SYSC_SYS_ACPU_CFG_EMPH_AENDMPH_Msk                   (0x000000FFUL)
#define R_SYSC_SYS_ACPU_CFG_EMPH_AENDMPH_Pos                   (0UL)
#define R_SYSC_SYS_ACPU_CFG_RVAL0_RVBARADDRL0_Msk              (0xFFFFFFFCUL)
#define R_SYSC_SYS_ACPU_CFG_RVAL0_RVBARADDRL0_Pos              (2UL)
#define R_SYSC_SYS_ACPU_CFG_RVAH0_RVBARADDRH0_Msk              (0x000000FFUL)
#define R_SYSC_SYS_ACPU_CFG_RVAH0_RVBARADDRH0_Pos              (0UL)
#define R_SYSC_SYS_ACPU_CFG_RVAL1_RVBARADDRL1_Msk              (0xFFFFFFFCUL)
#define R_SYSC_SYS_ACPU_CFG_RVAL1_RVBARADDRL1_Pos              (2UL)
#define R_SYSC_SYS_ACPU_CFG_RVAH1_RVBARADDRH1_Msk              (0x000000FFUL)
#define R_SYSC_SYS_ACPU_CFG_RVAH1_RVBARADDRH1_Pos              (0UL)
#define R_SYSC_SYS_ACPU_CFG_RVAL2_RVBARADDRL2_Msk              (0xFFFFFFFCUL)
#define R_SYSC_SYS_ACPU_CFG_RVAL2_RVBARADDRL2_Pos              (2UL)
#define R_SYSC_SYS_ACPU_CFG_RVAH2_RVBARADDRH2_Msk              (0x000000FFUL)
#define R_SYSC_SYS_ACPU_CFG_RVAH2_RVBARADDRH2_Pos              (0UL)
#define R_SYSC_SYS_ACPU_CFG_RVAL3_RVBARADDRL3_Msk              (0xFFFFFFFCUL)
#define R_SYSC_SYS_ACPU_CFG_RVAL3_RVBARADDRL3_Pos              (2UL)
#define R_SYSC_SYS_ACPU_CFG_RVAH3_RVBARADDRH3_Msk              (0x000000FFUL)
#define R_SYSC_SYS_ACPU_CFG_RVAH3_RVBARADDRH3_Pos              (0UL)
#define R_SYSC_SYS_RCPU_CONFIG1_MFILTEREN_Msk                  (0x00000004UL)
#define R_SYSC_SYS_RCPU_CONFIG1_MFILTEREN_Pos                  (2UL)
#define R_SYSC_SYS_RCPU_CONFIG1_ITCMECCEN_Msk                  (0x00000008UL)
#define R_SYSC_SYS_RCPU_CONFIG1_ITCMECCEN_Pos                  (3UL)
#define R_SYSC_SYS_RCPU_CONFIG2_MFILTERSTART_Msk               (0x00000FFFUL)
#define R_SYSC_SYS_RCPU_CONFIG2_MFILTERSTART_Pos               (0UL)
#define R_SYSC_SYS_RCPU_CONFIG2_MFILTEREND_Msk                 (0x0FFF0000UL)
#define R_SYSC_SYS_RCPU_CONFIG2_MFILTEREND_Pos                 (16UL)
#define R_SYSC_SYS_RCPU_CONFIG3_PERIPHBASE_Msk                 (0xFFFFE000UL)
#define R_SYSC_SYS_RCPU_CONFIG3_PERIPHBASE_Pos                 (13UL)
#define R_SYSC_SYS_RCPU_CONFIG4_PFILTERSTART_Msk               (0x00000FFFUL)
#define R_SYSC_SYS_RCPU_CONFIG4_PFILTERSTART_Pos               (0UL)
#define R_SYSC_SYS_RCPU_CONFIG4_PFILTEREND_Msk                 (0x0FFF0000UL)
#define R_SYSC_SYS_RCPU_CONFIG4_PFILTEREND_Pos                 (16UL)
#define R_SYSC_SYS_RCPU_CORESTATUS_SMPnAMP_Msk                 (0x00000003UL)
#define R_SYSC_SYS_RCPU_CORESTATUS_SMPnAMP_Pos                 (0UL)
#define R_SYSC_SYS_RCPU_CORESTATUS_PMUPRIV_Msk                 (0x00000300UL)
#define R_SYSC_SYS_RCPU_CORESTATUS_PMUPRIV_Pos                 (8UL)
#define R_SYSC_SYS_RCPU_CORESTATUS_PWRCTLO0_Msk                (0x00300000UL)
#define R_SYSC_SYS_RCPU_CORESTATUS_PWRCTLO0_Pos                (20UL)
#define R_SYSC_SYS_RCPU_CORESTATUS_PWRCTLO1_Msk                (0x00C00000UL)
#define R_SYSC_SYS_RCPU_CORESTATUS_PWRCTLO1_Pos                (22UL)
#define R_SYSC_SYS_RCPU_CORESTATUS_SCUIDLE_Msk                 (0x01000000UL)
#define R_SYSC_SYS_RCPU_CORESTATUS_SCUIDLE_Pos                 (24UL)
#define R_SYSC_SYS_MCPU_CFG2_INITSVTOR_Msk                     (0xFFFFFF80UL)
#define R_SYSC_SYS_MCPU_CFG2_INITSVTOR_Pos                     (7UL)
#define R_SYSC_SYS_MCPU_CFG3_INITNSVTOR_Msk                    (0xFFFFFF80UL)
#define R_SYSC_SYS_MCPU_CFG3_INITNSVTOR_Pos                    (7UL)
#define R_SYSC_SYS_MCPU_CFG4_IDAUZERONS_Msk                    (0x00000001UL)
#define R_SYSC_SYS_MCPU_CFG4_IDAUZERONS_Pos                    (0UL)
#define R_SYSC_SYS_MCPU_CFG5_LOCKSVTAIRCR_Msk                  (0x00000001UL)
#define R_SYSC_SYS_MCPU_CFG5_LOCKSVTAIRCR_Pos                  (0UL)
#define R_SYSC_SYS_MCPU_CFG5_LOCKNSVTOR_Msk                    (0x00000002UL)
#define R_SYSC_SYS_MCPU_CFG5_LOCKNSVTOR_Pos                    (1UL)
#define R_SYSC_SYS_SPI_STAADDCS0_XSPI_STARTADDRCS0_Msk         (0xFFFFFFFFUL)
#define R_SYSC_SYS_SPI_STAADDCS0_XSPI_STARTADDRCS0_Pos         (0UL)
#define R_SYSC_SYS_SPI_ENDADDCS0_XSPI_ENDADDRCS0_Msk           (0xFFFFFFFFUL)
#define R_SYSC_SYS_SPI_ENDADDCS0_XSPI_ENDADDRCS0_Pos           (0UL)
#define R_SYSC_SYS_SPI_STAADDCS1_XSPI_STARTADDRCS1_Msk         (0xFFFFFFFFUL)
#define R_SYSC_SYS_SPI_STAADDCS1_XSPI_STARTADDRCS1_Pos         (0UL)
#define R_SYSC_SYS_SPI_ENDADDCS1_XSPI_ENDADDRCS1_Msk           (0xFFFFFFFFUL)
#define R_SYSC_SYS_SPI_ENDADDCS1_XSPI_ENDADDRCS1_Pos           (0UL)
#define R_SYSC_SYS_SRAM0_ECC_VECCEN_Msk                        (0x00000001UL)
#define R_SYSC_SYS_SRAM0_ECC_VECCEN_Pos                        (0UL)
#define R_SYSC_SYS_SRAM0_EN_VCEN_Msk                           (0x00000001UL)
#define R_SYSC_SYS_SRAM0_EN_VCEN_Pos                           (0UL)
#define R_SYSC_SYS_SRAM0_EN_VLWEN_Msk                          (0x00000002UL)
#define R_SYSC_SYS_SRAM0_EN_VLWEN_Pos                          (1UL)
#define R_SYSC_SYS_SRAM1_ECC_VECCEN_Msk                        (0x00000001UL)
#define R_SYSC_SYS_SRAM1_ECC_VECCEN_Pos                        (0UL)
#define R_SYSC_SYS_SRAM1_EN_VCEN_Msk                           (0x00000001UL)
#define R_SYSC_SYS_SRAM1_EN_VCEN_Pos                           (0UL)
#define R_SYSC_SYS_SRAM1_EN_VLWEN_Msk                          (0x00000002UL)
#define R_SYSC_SYS_SRAM1_EN_VLWEN_Pos                          (1UL)
#define R_SYSC_SYS_SRAM2_ECC_VECCEN_Msk                        (0x00000001UL)
#define R_SYSC_SYS_SRAM2_ECC_VECCEN_Pos                        (0UL)
#define R_SYSC_SYS_SRAM2_EN_VCEN_Msk                           (0x00000001UL)
#define R_SYSC_SYS_SRAM2_EN_VCEN_Pos                           (0UL)
#define R_SYSC_SYS_SRAM2_EN_VLWEN_Msk                          (0x00000002UL)
#define R_SYSC_SYS_SRAM2_EN_VLWEN_Pos                          (1UL)
#define R_SYSC_SYS_SRAM3_ECC_VECCEN_Msk                        (0x00000001UL)
#define R_SYSC_SYS_SRAM3_ECC_VECCEN_Pos                        (0UL)
#define R_SYSC_SYS_SRAM3_EN_VCEN_Msk                           (0x00000001UL)
#define R_SYSC_SYS_SRAM3_EN_VCEN_Pos                           (0UL)
#define R_SYSC_SYS_SRAM3_EN_VLWEN_Msk                          (0x00000002UL)
#define R_SYSC_SYS_SRAM3_EN_VLWEN_Pos                          (1UL)
#define R_SYSC_SYS_SRAM4_ECC_VECCEN_Msk                        (0x00000001UL)
#define R_SYSC_SYS_SRAM4_ECC_VECCEN_Pos                        (0UL)
#define R_SYSC_SYS_SRAM4_EN_VCEN_Msk                           (0x00000001UL)
#define R_SYSC_SYS_SRAM4_EN_VCEN_Pos                           (0UL)
#define R_SYSC_SYS_SRAM4_EN_VLWEN_Msk                          (0x00000002UL)
#define R_SYSC_SYS_SRAM4_EN_VLWEN_Pos                          (1UL)
#define R_SYSC_SYS_SRAM5_ECC_VECCEN_Msk                        (0x00000001UL)
#define R_SYSC_SYS_SRAM5_ECC_VECCEN_Pos                        (0UL)
#define R_SYSC_SYS_SRAM5_EN_VCEN_Msk                           (0x00000001UL)
#define R_SYSC_SYS_SRAM5_EN_VCEN_Pos                           (0UL)
#define R_SYSC_SYS_SRAM5_EN_VLWEN_Msk                          (0x00000002UL)
#define R_SYSC_SYS_SRAM5_EN_VLWEN_Pos                          (1UL)
#define R_SYSC_SYS_SRAM6_ECC_VECCEN_Msk                        (0x00000001UL)
#define R_SYSC_SYS_SRAM6_ECC_VECCEN_Pos                        (0UL)
#define R_SYSC_SYS_SRAM6_EN_VCEN_Msk                           (0x00000001UL)
#define R_SYSC_SYS_SRAM6_EN_VCEN_Pos                           (0UL)
#define R_SYSC_SYS_SRAM6_EN_VLWEN_Msk                          (0x00000002UL)
#define R_SYSC_SYS_SRAM6_EN_VLWEN_Pos                          (1UL)
#define R_SYSC_SYS_SRAM7_ECC_VECCEN_Msk                        (0x00000001UL)
#define R_SYSC_SYS_SRAM7_ECC_VECCEN_Pos                        (0UL)
#define R_SYSC_SYS_SRAM7_EN_VCEN_Msk                           (0x00000001UL)
#define R_SYSC_SYS_SRAM7_EN_VCEN_Pos                           (0UL)
#define R_SYSC_SYS_SRAM7_EN_VLWEN_Msk                          (0x00000002UL)
#define R_SYSC_SYS_SRAM7_EN_VLWEN_Pos                          (1UL)
#define R_SYSC_SYS_SRAM8_ECC_VECCEN_Msk                        (0x00000001UL)
#define R_SYSC_SYS_SRAM8_ECC_VECCEN_Pos                        (0UL)
#define R_SYSC_SYS_SRAM8_EN_VCEN_Msk                           (0x00000001UL)
#define R_SYSC_SYS_SRAM8_EN_VCEN_Pos                           (0UL)
#define R_SYSC_SYS_SRAM8_EN_VLWEN_Msk                          (0x00000002UL)
#define R_SYSC_SYS_SRAM8_EN_VLWEN_Pos                          (1UL)
#define R_SYSC_SYS_SRAM9_ECC_VECCEN_Msk                        (0x00000001UL)
#define R_SYSC_SYS_SRAM9_ECC_VECCEN_Pos                        (0UL)
#define R_SYSC_SYS_SRAM9_EN_VCEN_Msk                           (0x00000001UL)
#define R_SYSC_SYS_SRAM9_EN_VCEN_Pos                           (0UL)
#define R_SYSC_SYS_SRAM9_EN_VLWEN_Msk                          (0x00000002UL)
#define R_SYSC_SYS_SRAM9_EN_VLWEN_Pos                          (1UL)
#define R_SYSC_SYS_SRAM10_ECC_VECCEN_Msk                       (0x00000001UL)
#define R_SYSC_SYS_SRAM10_ECC_VECCEN_Pos                       (0UL)
#define R_SYSC_SYS_SRAM10_EN_VCEN_Msk                          (0x00000001UL)
#define R_SYSC_SYS_SRAM10_EN_VCEN_Pos                          (0UL)
#define R_SYSC_SYS_SRAM10_EN_VLWEN_Msk                         (0x00000002UL)
#define R_SYSC_SYS_SRAM10_EN_VLWEN_Pos                         (1UL)
#define R_SYSC_SYS_SRAM11_ECC_VECCEN_Msk                       (0x00000001UL)
#define R_SYSC_SYS_SRAM11_ECC_VECCEN_Pos                       (0UL)
#define R_SYSC_SYS_SRAM11_EN_VCEN_Msk                          (0x00000001UL)
#define R_SYSC_SYS_SRAM11_EN_VCEN_Pos                          (0UL)
#define R_SYSC_SYS_SRAM11_EN_VLWEN_Msk                         (0x00000002UL)
#define R_SYSC_SYS_SRAM11_EN_VLWEN_Pos                         (1UL)
#define R_SYSC_SYS_WDT0_CTRL_bp_halted_Msk                     (0x00000001UL)
#define R_SYSC_SYS_WDT0_CTRL_bp_halted_Pos                     (0UL)
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOPMASK_Msk                   (0x00010000UL)
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOPMASK_Pos                   (16UL)
#define R_SYSC_SYS_WDT1_CTRL_bp_halted_Msk                     (0x00000001UL)
#define R_SYSC_SYS_WDT1_CTRL_bp_halted_Pos                     (0UL)
#define R_SYSC_SYS_WDT1_CTRL_WDTSTOPMASK_Msk                   (0x00010000UL)
#define R_SYSC_SYS_WDT1_CTRL_WDTSTOPMASK_Pos                   (16UL)
#define R_SYSC_SYS_WDT2_CTRL_bp_halted_Msk                     (0x00000001UL)
#define R_SYSC_SYS_WDT2_CTRL_bp_halted_Pos                     (0UL)
#define R_SYSC_SYS_WDT2_CTRL_WDTSTOPMASK_Msk                   (0x00010000UL)
#define R_SYSC_SYS_WDT2_CTRL_WDTSTOPMASK_Pos                   (16UL)
#define R_SYSC_SYS_WDT3_CTRL_bp_halted_Msk                     (0x00000001UL)
#define R_SYSC_SYS_WDT3_CTRL_bp_halted_Pos                     (0UL)
#define R_SYSC_SYS_WDT3_CTRL_WDTSTOPMASK_Msk                   (0x00010000UL)
#define R_SYSC_SYS_WDT3_CTRL_WDTSTOPMASK_Pos                   (16UL)
#define R_SYSC_SYS_GBETH0_CFG_MAC_SPEED_Msk                    (0x00000003UL)
#define R_SYSC_SYS_GBETH0_CFG_MAC_SPEED_Pos                    (0UL)
#define R_SYSC_SYS_GBETH0_CFG_PHY_INTF_TYPE_Msk                (0x00070000UL)
#define R_SYSC_SYS_GBETH0_CFG_PHY_INTF_TYPE_Pos                (16UL)
#define R_SYSC_SYS_GBETH1_CFG_MAC_SPEED_Msk                    (0x00000003UL)
#define R_SYSC_SYS_GBETH1_CFG_MAC_SPEED_Pos                    (0UL)
#define R_SYSC_SYS_GBETH1_CFG_PHY_INTF_TYPE_Msk                (0x00070000UL)
#define R_SYSC_SYS_GBETH1_CFG_PHY_INTF_TYPE_Pos                (16UL)
#define R_SYSC_SYS_PCIE_INTX_CH0_INTX_EP_F0_Msk                (0x00000001UL)
#define R_SYSC_SYS_PCIE_INTX_CH0_INTX_EP_F0_Pos                (0UL)
#define R_SYSC_SYS_PCIE_INTX_CH0_INTX_EP_F1_Msk                (0x00000002UL)
#define R_SYSC_SYS_PCIE_INTX_CH0_INTX_EP_F1_Pos                (1UL)
#define R_SYSC_SYS_PCIE_MSI1_CH0_UI_EXTMSI_VAL0_Msk            (0x00000001UL)
#define R_SYSC_SYS_PCIE_MSI1_CH0_UI_EXTMSI_VAL0_Pos            (0UL)
#define R_SYSC_SYS_PCIE_MSI1_CH0_UI_EXTMSI_VAL1_Msk            (0x00000002UL)
#define R_SYSC_SYS_PCIE_MSI1_CH0_UI_EXTMSI_VAL1_Pos            (1UL)
#define R_SYSC_SYS_PCIE_MSI1_CH0_UI_EXTMSI_VAL2_Msk            (0x00000004UL)
#define R_SYSC_SYS_PCIE_MSI1_CH0_UI_EXTMSI_VAL2_Pos            (2UL)
#define R_SYSC_SYS_PCIE_MSI1_CH0_UI_EXTMSI_VAL3_Msk            (0x00000008UL)
#define R_SYSC_SYS_PCIE_MSI1_CH0_UI_EXTMSI_VAL3_Pos            (3UL)
#define R_SYSC_SYS_PCIE_MSI1_CH0_UI_EXTMSI_VAL4_Msk            (0x00000010UL)
#define R_SYSC_SYS_PCIE_MSI1_CH0_UI_EXTMSI_VAL4_Pos            (4UL)
#define R_SYSC_SYS_PCIE_MSI2_CH0_UI_EXTMSI_VEC0_Msk            (0x0000001FUL)
#define R_SYSC_SYS_PCIE_MSI2_CH0_UI_EXTMSI_VEC0_Pos            (0UL)
#define R_SYSC_SYS_PCIE_MSI2_CH0_UI_EXTMSI_VEC1_Msk            (0x00001F00UL)
#define R_SYSC_SYS_PCIE_MSI2_CH0_UI_EXTMSI_VEC1_Pos            (8UL)
#define R_SYSC_SYS_PCIE_MSI2_CH0_UI_EXTMSI_VEC2_Msk            (0x001F0000UL)
#define R_SYSC_SYS_PCIE_MSI2_CH0_UI_EXTMSI_VEC2_Pos            (16UL)
#define R_SYSC_SYS_PCIE_MSI2_CH0_UI_EXTMSI_VEC3_Msk            (0x1F000000UL)
#define R_SYSC_SYS_PCIE_MSI2_CH0_UI_EXTMSI_VEC3_Pos            (24UL)
#define R_SYSC_SYS_PCIE_MSI3_CH0_UI_EXTMSI_VEC_Msk             (0x0000001FUL)
#define R_SYSC_SYS_PCIE_MSI3_CH0_UI_EXTMSI_VEC_Pos             (0UL)
#define R_SYSC_SYS_PCIE_MSI4_CH0_UI_EXTMSI_FUNC0_Msk           (0x00000007UL)
#define R_SYSC_SYS_PCIE_MSI4_CH0_UI_EXTMSI_FUNC0_Pos           (0UL)
#define R_SYSC_SYS_PCIE_MSI4_CH0_UI_EXTMSI_FUNC1_Msk           (0x00000700UL)
#define R_SYSC_SYS_PCIE_MSI4_CH0_UI_EXTMSI_FUNC1_Pos           (8UL)
#define R_SYSC_SYS_PCIE_MSI4_CH0_UI_EXTMSI_FUNC2_Msk           (0x00070000UL)
#define R_SYSC_SYS_PCIE_MSI4_CH0_UI_EXTMSI_FUNC2_Pos           (16UL)
#define R_SYSC_SYS_PCIE_MSI4_CH0_UI_EXTMSI_FUNC3_Msk           (0x07000000UL)
#define R_SYSC_SYS_PCIE_MSI4_CH0_UI_EXTMSI_FUNC3_Pos           (24UL)
#define R_SYSC_SYS_PCIE_MSI5_CH0_UI_EXTMSI_FUNC4_Msk           (0x00000007UL)
#define R_SYSC_SYS_PCIE_MSI5_CH0_UI_EXTMSI_FUNC4_Pos           (0UL)
#define R_SYSC_SYS_PCIE_PME_CH0_PME_TIM_Msk                    (0x00000001UL)
#define R_SYSC_SYS_PCIE_PME_CH0_PME_TIM_Pos                    (0UL)
#define R_SYSC_SYS_PCIE_PME_CH0_CFG_PMCSR_PME_STATUS_F0_Msk    (0x00000100UL)
#define R_SYSC_SYS_PCIE_PME_CH0_CFG_PMCSR_PME_STATUS_F0_Pos    (8UL)
#define R_SYSC_SYS_PCIE_PME_CH0_CFG_PMCSR_PME_STATUS_F1_Msk    (0x00000200UL)
#define R_SYSC_SYS_PCIE_PME_CH0_CFG_PMCSR_PME_STATUS_F1_Pos    (9UL)
#define R_SYSC_SYS_PCIE_ACK_CH0_TURN_OFF_EVENT_ACK_Msk         (0x00000001UL)
#define R_SYSC_SYS_PCIE_ACK_CH0_TURN_OFF_EVENT_ACK_Pos         (0UL)
#define R_SYSC_SYS_PCIE_ACK_CH0_D3_ECENT_ACK_F0_Msk            (0x00000100UL)
#define R_SYSC_SYS_PCIE_ACK_CH0_D3_ECENT_ACK_F0_Pos            (8UL)
#define R_SYSC_SYS_PCIE_ACK_CH0_D3_ECENT_ACK_F1_Msk            (0x00000200UL)
#define R_SYSC_SYS_PCIE_ACK_CH0_D3_ECENT_ACK_F1_Pos            (9UL)
#define R_SYSC_SYS_PCIE_MISC_CH0_ALLOW_ENTER_L1_Msk            (0x00000001UL)
#define R_SYSC_SYS_PCIE_MISC_CH0_ALLOW_ENTER_L1_Pos            (0UL)
#define R_SYSC_SYS_PCIE_MISC_CH0_FLR_RESET_Msk                 (0x00030000UL)
#define R_SYSC_SYS_PCIE_MISC_CH0_FLR_RESET_Pos                 (16UL)
#define R_SYSC_SYS_PCIE_MISC_CH0_FLR_REQ_Msk                   (0x000C0000UL)
#define R_SYSC_SYS_PCIE_MISC_CH0_FLR_REQ_Pos                   (18UL)
#define R_SYSC_SYS_PCIE_MODE_CH0_MODE_PORT_Msk                 (0x00000001UL)
#define R_SYSC_SYS_PCIE_MODE_CH0_MODE_PORT_Pos                 (0UL)
#define R_SYSC_SYS_PCIE_INTX_CH1_INTX_EP_F0_Msk                (0x00000001UL)
#define R_SYSC_SYS_PCIE_INTX_CH1_INTX_EP_F0_Pos                (0UL)
#define R_SYSC_SYS_PCIE_INTX_CH1_INTX_EP_F1_Msk                (0x00000002UL)
#define R_SYSC_SYS_PCIE_INTX_CH1_INTX_EP_F1_Pos                (1UL)
#define R_SYSC_SYS_PCIE_MSI1_CH1_UI_EXTMSI_VAL0_Msk            (0x00000001UL)
#define R_SYSC_SYS_PCIE_MSI1_CH1_UI_EXTMSI_VAL0_Pos            (0UL)
#define R_SYSC_SYS_PCIE_MSI1_CH1_UI_EXTMSI_VAL1_Msk            (0x00000002UL)
#define R_SYSC_SYS_PCIE_MSI1_CH1_UI_EXTMSI_VAL1_Pos            (1UL)
#define R_SYSC_SYS_PCIE_MSI1_CH1_UI_EXTMSI_VAL2_Msk            (0x00000004UL)
#define R_SYSC_SYS_PCIE_MSI1_CH1_UI_EXTMSI_VAL2_Pos            (2UL)
#define R_SYSC_SYS_PCIE_MSI1_CH1_UI_EXTMSI_VAL3_Msk            (0x00000008UL)
#define R_SYSC_SYS_PCIE_MSI1_CH1_UI_EXTMSI_VAL3_Pos            (3UL)
#define R_SYSC_SYS_PCIE_MSI1_CH1_UI_EXTMSI_VAL4_Msk            (0x00000010UL)
#define R_SYSC_SYS_PCIE_MSI1_CH1_UI_EXTMSI_VAL4_Pos            (4UL)
#define R_SYSC_SYS_PCIE_MSI2_CH1_UI_EXTMSI_VEC0_Msk            (0x0000001FUL)
#define R_SYSC_SYS_PCIE_MSI2_CH1_UI_EXTMSI_VEC0_Pos            (0UL)
#define R_SYSC_SYS_PCIE_MSI2_CH1_UI_EXTMSI_VEC1_Msk            (0x00001F00UL)
#define R_SYSC_SYS_PCIE_MSI2_CH1_UI_EXTMSI_VEC1_Pos            (8UL)
#define R_SYSC_SYS_PCIE_MSI2_CH1_UI_EXTMSI_VEC2_Msk            (0x001F0000UL)
#define R_SYSC_SYS_PCIE_MSI2_CH1_UI_EXTMSI_VEC2_Pos            (16UL)
#define R_SYSC_SYS_PCIE_MSI2_CH1_UI_EXTMSI_VEC3_Msk            (0x1F000000UL)
#define R_SYSC_SYS_PCIE_MSI2_CH1_UI_EXTMSI_VEC3_Pos            (24UL)
#define R_SYSC_SYS_PCIE_MSI3_CH1_UI_EXTMSI_VEC4_Msk            (0x0000001FUL)
#define R_SYSC_SYS_PCIE_MSI3_CH1_UI_EXTMSI_VEC4_Pos            (0UL)
#define R_SYSC_SYS_PCIE_MSI4_CH1_UI_EXTMSI_FUNC0_Msk           (0x00000007UL)
#define R_SYSC_SYS_PCIE_MSI4_CH1_UI_EXTMSI_FUNC0_Pos           (0UL)
#define R_SYSC_SYS_PCIE_MSI4_CH1_UI_EXTMSI_FUNC1_Msk           (0x00000700UL)
#define R_SYSC_SYS_PCIE_MSI4_CH1_UI_EXTMSI_FUNC1_Pos           (8UL)
#define R_SYSC_SYS_PCIE_MSI4_CH1_UI_EXTMSI_FUNC2_Msk           (0x00070000UL)
#define R_SYSC_SYS_PCIE_MSI4_CH1_UI_EXTMSI_FUNC2_Pos           (16UL)
#define R_SYSC_SYS_PCIE_MSI4_CH1_UI_EXTMSI_FUNC3_Msk           (0x07000000UL)
#define R_SYSC_SYS_PCIE_MSI4_CH1_UI_EXTMSI_FUNC3_Pos           (24UL)
#define R_SYSC_SYS_PCIE_MSI5_CH1_UI_EXTMSI_FUNC40_Msk          (0x00000001UL)
#define R_SYSC_SYS_PCIE_MSI5_CH1_UI_EXTMSI_FUNC40_Pos          (0UL)
#define R_SYSC_SYS_PCIE_MSI5_CH1_UI_EXTMSI_FUNC4_Msk           (0x00000006UL)
#define R_SYSC_SYS_PCIE_MSI5_CH1_UI_EXTMSI_FUNC4_Pos           (1UL)
#define R_SYSC_SYS_PCIE_PME_CH1_PME_TIM_Msk                    (0x00000001UL)
#define R_SYSC_SYS_PCIE_PME_CH1_PME_TIM_Pos                    (0UL)
#define R_SYSC_SYS_PCIE_PME_CH1_CFG_PMCSR_PME_STATUS_F0_Msk    (0x00000100UL)
#define R_SYSC_SYS_PCIE_PME_CH1_CFG_PMCSR_PME_STATUS_F0_Pos    (8UL)
#define R_SYSC_SYS_PCIE_PME_CH1_CFG_PMCSR_PME_STATUS_F1_Msk    (0x00000200UL)
#define R_SYSC_SYS_PCIE_PME_CH1_CFG_PMCSR_PME_STATUS_F1_Pos    (9UL)
#define R_SYSC_SYS_PCIE_ACK_CH1_TURN_OFF_EVENT_ACK_Msk         (0x00000001UL)
#define R_SYSC_SYS_PCIE_ACK_CH1_TURN_OFF_EVENT_ACK_Pos         (0UL)
#define R_SYSC_SYS_PCIE_ACK_CH1_D3_ECENT_ACK_F0_Msk            (0x00000100UL)
#define R_SYSC_SYS_PCIE_ACK_CH1_D3_ECENT_ACK_F0_Pos            (8UL)
#define R_SYSC_SYS_PCIE_ACK_CH1_D3_ECENT_ACK_F1_Msk            (0x00000200UL)
#define R_SYSC_SYS_PCIE_ACK_CH1_D3_ECENT_ACK_F1_Pos            (9UL)
#define R_SYSC_SYS_PCIE_MISC_CH1_ALLOW_ENTER_L1_Msk            (0x00000001UL)
#define R_SYSC_SYS_PCIE_MISC_CH1_ALLOW_ENTER_L1_Pos            (0UL)
#define R_SYSC_SYS_PCIE_MISC_CH1_FLR_RESET_Msk                 (0x00030000UL)
#define R_SYSC_SYS_PCIE_MISC_CH1_FLR_RESET_Pos                 (16UL)
#define R_SYSC_SYS_PCIE_MISC_CH1_FLR_REQ_Msk                   (0x000C0000UL)
#define R_SYSC_SYS_PCIE_MISC_CH1_FLR_REQ_Pos                   (18UL)
#define R_SYSC_SYS_PCIE_MODE_CH1_MODE_PORT_Msk                 (0x00000001UL)
#define R_SYSC_SYS_PCIE_MODE_CH1_MODE_PORT_Pos                 (0UL)
#define R_SYSC_SYS_PCIE_MODE_CH1_LINK_MASTER_Msk               (0x00000300UL)
#define R_SYSC_SYS_PCIE_MODE_CH1_LINK_MASTER_Pos               (8UL)
#define R_SYSC_SYS_PCIE_MODE_LINK_MASTER_Msk                   (0x00000300UL)
#define R_SYSC_SYS_PCIE_MODE_LINK_MASTER_Pos                   (8UL)
#define R_SYSC_SYS_ADC_CFG_sy_mstp_ada_Msk                     (0x00000001UL)
#define R_SYSC_SYS_ADC_CFG_sy_mstp_ada_Pos                     (0UL)
#define R_SYSC_SYS_GPREG_0_CPREG0_Msk                          (0xFFFFFFFFUL)
#define R_SYSC_SYS_GPREG_0_CPREG0_Pos                          (0UL)
#define R_SYSC_SYS_GPREG_1_CPREG1_Msk                          (0xFFFFFFFFUL)
#define R_SYSC_SYS_GPREG_1_CPREG1_Pos                          (0UL)
#define R_SYSC_SYS_GPREG_2_CPREG2_Msk                          (0xFFFFFFFFUL)
#define R_SYSC_SYS_GPREG_2_CPREG2_Pos                          (0UL)
#define R_SYSC_SYS_GPREG_3_CPREG3_Msk                          (0xFFFFFFFFUL)
#define R_SYSC_SYS_GPREG_3_CPREG3_Pos                          (0UL)

#endif
